Many electronic products need various amounts of memory to store information, e.g. data. One common type of high speed, low cost memory includes dynamic random access memory (DRAM) comprised of individual DRAM cells arranged in arrays. Each DRAM cell includes an access transistor, e.g. a metal oxide semiconducting field effect transistor (MOSFET), coupled to a capacitor cell, and for that reason is referred to as a 1T1C cell. Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The memory cells are referred to as dynamic because they must also be refreshed periodically to maintain data integrity. The access transistors of the memory cells connect to internal signal lines, referred to as bit or digit lines. The gates of the access transistors of the memory cells connect to addressing lines, referred to as wordlines. The wordline selects the transistor to be turned on, and the bit line is thus coupled to the capacitor cell via the induced channel of the transistor. The bit line voltage is increased or decreased a small amount depending on the charge stored in the capacitor cell. These small changes are amplified by the sense amp to a voltage level corresponding to a logic level 1 or logic level 0
During a read or refresh operation, each sense amplifier compares the voltage level on the bit line to be read with a known reference voltage, usually another bit line with a constant voltage, that is, a bit line whose voltage is not being affected by a capacitor cell. In the sensing operation, which is necessary to properly read the cell data and to refresh the memory cells, the two bit lines are first equalized to a reference voltage which is typically, but not limited to, one half of the supply voltage (Vcc). The voltage of the bit line to be read will increase or decrease depending on the charge stored on the cells capacitor. If the bitline being read corresponds to a logic level of 1, then the sense amplifier will increase the voltage on the bitline to Vcc, while decreasing the voltage on the reference bitline to 0, and vice versa if the bitline to be read corresponds to a logic level of 0.
With successive generations of DRAM chips, an emphasis continues to be placed on increasing array density and maximizing chip real estate, which increases the overall memory capacity of each memory device or decreases the overall size of each memory device.
One way to increase array density is to use an open bit line architecture. In this setting, each word line is connected to mbit transistors on every bit line, creating crosspoint-style arrays. The sense amplifiers are located between sub-arrays, and each sense amplifier compares bit line values of two bit lines, each bit line in the pair coming from separate sub-arrays. An alternative to the open bit line architecture is the folded bit line architecture, which requires more real estate to operate than the open bit line. In the folded bitline architecture, each wordline connects or forms a crosspoint with a memory cell transistor on every other bitline and must pass around memory cell transistors on the remaining bit lines. Sense amplifiers are placed at the edge of each array and connect to both true and complement bit lines coming from a single sub-array, thus the bitline and reference bitline are located next to each other. During a read operation, one of the bit lines connected to the sense amplifier is always rising to Vcc, while the other bitline connected to the same sense amplifier is always falling to 0. Thus, the folded bitline architecture has reduced bitline to substrate capacitive coupling in comparison with the open bit line architecture, due to a cancellation of the coupling effects by the opposite voltage levels of each bitline, but requires more area to operate.
In another effort to improve memory cell density, the capacitors can be formed within trenches, known as trench capacitors. The trenches must extend deep into the substrate, making the manufacturing process to form trench capacitors difficult. An alternative to this approach is to form the capacitor in another location, for example, in a stack configuration in which the capacitor is formed above the access transistor. These configurations however do not make effective use of the what would be the trench area of the cell, and thus leads to an overall larger memory array design.
For these reasons and others, what is needed is a method of reducing the substrate to bitline capacitive coupling created in the open bitline architecture, while striving to reduce the overall size of the device, thus increasing array density.